Portable electronic devices, such as a cellular phone, a notebook-size personal computer, and a personal data assistance (PDA), are required to be downsized and reduced in weight. Along with this, a mounting space for semiconductor chips to be used in those electronic devices is strictly limited, and there is a problem of high-density mounting of the semiconductor chips. In view of this, in recent years, there has been an attempt to perform high-density mounting of a semiconductor package by a three-dimensional mounting technology, that is, by laminating semiconductor chips on top of another and connecting the semiconductor chips through wiring.
In addition, a conventional wafer level package (WLP) is manufactured by forming bumps into a wafer shape and dicing the wafer into chips. However, the conventional WLP has problems in that it is difficult to increase the number of pins, and chipping and the like of semiconductor chips are liable to occur because the semiconductor chips are mounted in a state in which the back surfaces thereof are exposed.
Therefore, as a new WLP, a fan-out type WLP has been proposed. In the fan-out type WLP, it is possible to increase the number of pins, and chipping and the like of semiconductor chips can be prevented by protecting end portions of the semiconductor chips.
The manufacturing method of the fan-out type WLP includes the step of molding a plurality of semiconductor chips with a sealing material of a resin, to thereby form a substrate to be processed, followed by arranging wiring on one surface of the substrate to be processed, the step of forming solder bumps, and the like.
Those steps involve heat treatment at about 200° C. to about 300° C., and hence there is a risk in that the sealing material may be deformed, and the substrate to be processed may change in dimension. When the substrate to be processed changes in dimension, it becomes difficult to arrange wiring at high density on one surface of the substrate to be processed, and it is also difficult to form the solder bumps accurately. Further, when the ratio of the semiconductor chips within the substrate to be processed is small and the ratio of the sealing material within the substrate to be processed is large, such tendency becomes remarkable.